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linear lifepo 4 battery charger with power path and usb compatibility in lfcsp data sheet ADP5063 rev. 0 document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third p arties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their resp ective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 ? 2013 analog devices, inc. all rights reserved. technical support www.analog.com features default charging termination voltage at 3.6 v fully compatible with usb 3.0 and usb battery charging 1.2 compliance plan specification operating input voltage from 4 v to 6. 7 v tolerant input voltage from ?0.5 v to +20 v (usb vbus) fully programmable via i 2 c flexible digital control inputs up to 2.1 a current from an ac charger in ldo mode built - in current sensing and limiting as low as 55 m battery isolation fet between batte ry and charger output thermal regulation prevents over heating compliant with jeita1 and jeita 2 li - ion battery charging temperature specifications sys_en flag permits the system to be disabled until battery is at the minimum required level for guaranteed sy stem start - up 4 mm 4 mm lfcsp package applications single c ell lithium iron phosphate ( li fepo 4 ) portable equipment portable medical devices portable instrumentation devices portable consumer devices general description the ADP5063 charger is fully compliant with usb 3.0 and the usb battery charging 1.2 compliance plan specification , and enables charging via the mini usb vbus pin from a wall charger, car charger, or usb host port. the ADP5063 operates from a 4 v to 6.7 v input voltage range but is tolerant of voltages up to 20 v , thereby alleviating concerns about usb bus spik es during d isconnect ion or conn ect ion scenarios. the ADP5063 features an internal field effect transistor ( fet ) between the linear charger output and the battery. this permits battery isolation and, therefore , system powering under a dead battery or no battery scenario, which allows immediate system func tion up on connec tion to a usb power supply. based on the type of usb source, which is detected by an external usb det ection chip, the ADP5063 can be set to apply the correct current limit for optimal charging and usb compliance. the ADP5063 has three factory - programmable digital input/out - put pins that prov ide maximum flexibility for different systems. these digital input/output pins permit a combination of features , such as input current limits, charging enable and disable, charging current limits, and a dedicated interrupt output pin. typical application circuit figure 1 . vinx vbus ac or usb scl sda dig_io1 dig_io2 dig_io3 agnd + li-ion thr c3 22 f c1 100nf c4 10 f c2 22 f iso_sx iso_bx bat_sns ADP5063 sys_en system programmable iled vled cbp charger control block 1 1593-001
ADP5063 data sheet rev. 0 | page 2 of 44 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 general description ......................................................................... 1 typical application circuit ............................................................. 1 re vision history ............................................................................... 2 specifications ..................................................................................... 3 recommended input and output capacitances ...................... 6 i 2 c- compatible interface timing specifications ..................... 6 absolute maximum ratings ............................................................ 8 thermal resistance ...................................................................... 8 esd caution .................................................................................. 8 pin configuration and function descriptions ............................. 9 typical performance characteristics ........................................... 10 temperature characteristics ..................................................... 12 typical waveforms ..................................................................... 14 theory of operation ...................................................................... 15 summary of operation modes ................................................. 15 in troduction ................................................................................ 16 charger modes ............................................................................ 18 thermal management ............................................................... 21 battery isolation fet ................................................................. 21 battery detection ....................................................................... 21 battery pa ck temperature sensing .......................................... 22 i 2 c interface ................................................................................ 26 i 2 c register map ......................................................................... 27 register bit descriptions ........................................................... 28 ap plications information .............................................................. 36 external components ................................................................ 36 pcb layout guidelines .............................................................. 38 power dissipation and thermal considerations ....................... 39 charger power dissipation ....................................................... 39 junction temperature ................................................................ 39 factory - programmable options .................................................. 40 charger options ......................................................................... 40 i 2 c register defaults .................................................................. 41 digital input and output options ........................................... 41 packaging and ordering information ......................................... 43 outline dimensions ................................................................... 43 ordering g uide .......................................................................... 43 revision history 7 /13 rev ision 0: initial version
data sheet ADP5063 rev. 0 | page 3 of 44 specifications ? 40 c < t j < + 125c , v vin x = 5.0 v , r hot _rise < r thr < r cold _fall , v bat_sns = 3.6 v, v iso_b x = v bat_sns , c vin x = 10 f, c iso_s x = 22 f, c iso_b x = 22 f, c c bp = 10 0 nf , all registers are at default values, unless otherwise noted . table 1. parameter symbol min typ max unit test conditions/comments general parameters undervoltage locko ut v uvlo 2. 25 2. 35 2.5 v falling threshold, higher of v vinx or v bat_sns 1 hysteresis 50 100 150 mv hysteresis, higher of v vinx or v bat_sns rising 1 total input current i lim 74 92 100 ma nominal usb initialized current level 2 114 150 ma usb super speed 300 ma usb enumerated current level ( s pecification for china) 425 470 500 ma usb enumerated current level 900 ma dedicated charger input 1500 ma dedicated wall charger vinx current consumption i qvin 2 ma charging or ldo mode i qvin_ suspend 1 .0 1.8 m a dis_ ldo = high , t j = ?40c to +85c battery current consumption i qbatt 20 a ldo mode, v iso_s x > v bat_sns 5 a standby, includes iso_sx pin leakage, v vin x = 0 v, t j = ?40c to +85c 0.5 0.9 ma standby, b attery monitor active charger fast charge current constant current (cc) mode i chg 750 ma fast charge current accuracy ? 9 + 9 % i chg = 40 0 ma to 1300 ma , v iso_bx = 3.3 v, t j = 0c to 115c trickle charge current 2 i trk_dead 16 20 25 ma weak charge current 2 , 3 i chg_weak i trk_dead + i chg ma trickle to weak charge threshold dead battery v trk_dead 1.9 2.0 2.1 v v trk_dead < v bat_sns < v weak 2 , 4 hysteresis v trk_dead 100 mv on bat_sns 2 weak battery threshold weak to fast charge threshold v weak 2.89 3.0 3.11 v on bat_sns 2 , 4 v weak 100 mv battery termination voltage v trm 3.6 00 v termination voltage accuracy ? 0. 6 +0. 6 % on bat_sns, t j = 25c, i end = 52.5 ma 2 ? 1. 55 + 1 . 45 % t j = 0c to 115c 2 ? 1. 7 +1. 7 % t j = ? 40c to + 125c battery overvoltage threshold v batov v in ? 0. 075 v relative to vinx voltage, bat_sns rising charge complete current i end 1 5 52.5 98 ma v bat_sns = v trm charging complete current threshold accuracy 1 7 8 3 ma i end = 52.5 ma , t j = 0c to 115c 2 59 123 ma i end = 92.5 ma , t j = 0 c to 115c recharge voltage differential v rch 160 260 390 mv relative to v trm , bat_sns falling 2 battery node short threshold voltage 2 v bat_shr 2.2 2.4 2.5 v battery short detection current i trk_short 20 ma i trk_short = i trk_dead 2 charging start voltage limit v chg_vlim 3.1 3.2 3.3 v voltage limit is not active by default charging soft start current i chg_start 185 260 365 ma v bat_sns > v trk_dead charging soft start time t chg_start 3 m s
ADP5063 data sheet rev. 0 | page 4 of 44 parameter symbol min typ max unit test conditions/comments battery isolation fet pin to pin resistance between iso_sx and iso_bx r dson _ iso 5 5 8 9 m o n battery supplement mode, vinx = 0 v, v iso_bx = 3.6 v, i iso_b x = 500 ma regulated system voltage: v bat low v iso_sfc 3.6 3.8 4.0 v vtrm [5:0] programming 4.00 v 3. 2 3. 4 3. 5 v vtrm [5:0] programming < 4.00 v battery supplementary threshold v thiso 0 5 12 mv v iso_s x < v iso_bx , system voltage rising ldo and high voltage blocking regulated system voltage v iso_strk 4.214 4.3 4.386 v vsystem [2:0] = 000 (binary) = 4.3 v, i iso_s x = 100 ma, ldo mode 2 load regulation ? 0. 56 %/a i iso_s x = 0 m a to 1 5 00 m a high voltage blocking fet (ldo fet) on resistance r ds(on)hv 3 30 4 8 5 m i v in x = 500 ma maximum output current 2.1 a v iso_sx = 4.3 v, ldo mode vinx input voltage, good threshold rising v vin_ok_rise 3.75 3.9 4.0 v vinx falling v vin_ok_fall 3.6 3.7 v vinx input overv oltage threshold v vin_ov 6.7 6.9 7.2 v hysteresis v vin_ov 0.1 v vinx transition timing t vin_rise 10 s minimum rise time for vinx from 5 v to 20 v t vin_fall 10 s minimum fall time for vinx from 4 v to 0 v thermal control isothermal charging temperature t lim 115 c thermal early warning temperature t sdl 130 c thermal shutdown temperature t sd 140 c t j rising 110 c t j falling thermistor control thermistor current 10,000 ntc (negative temperature coefficient) resistor i ntc_10k 400 a 100,000 ntc resistor i ntc_100k 40 a thermistor capacitance c ntc 100 pf cold temperature threshold t ntc_cold 0 c no battery charging occurs resistance thresholds cool to cold resistance r cold_fall 20,500 25,600 30,720 cold to cool resistance r cold_rise 24,400 hot temperature threshold t ntc_hot 60 c no battery charging occurs resistance thresholds hot to typical resistance r hot_fall 3700 typical to hot resistance r hot_rise 2750 3350 3950 jeita1 l i - ion battery charging specification defaults 5 jeita cold temperature t jeita_cold 0 c no battery charging occurs resistance thresholds cool to cold resistance r cold_fall 20,500 25,600 30,720 cold to cool resistance r cold_rise 24,400 jeita cool temperature t jeita_cool 10 c battery charging occurs at 50% of programmed level resistance thresholds typical to cool resistance r typ_fall 13,200 16,5 00 19,800 cool to typical resistance r typ_rise 15,900 jeita warm temperature t jeita_warm 45 c battery termination voltage (v trm ) is reduced by 100 mv resistance thresholds warm to typica l resistance r warm_fall 5800 typical to warm resistance r warm_rise 4260 5200 6140
data sheet ADP5063 rev. 0 | page 5 of 44 parameter symbol min typ max unit test conditions/comments jeita hot temperature t jeita_hot 60 c no battery charging occurs resistance thresholds hot to warm resistance r hot_fall 3700 warm to hot resistance r hot_rise 2750 3350 3950 jeita2 l i - ion battery charging specification defaults jeita cold temperature t jeita_cold 0 c no battery charging occurs resistance thresholds cool to cold resistance r cold_fall 20,500 25,600 30,720 cold to cool resistance r cold_rise 24,400 jeita cool temperature t jeita_cool 10 c battery termination voltage (v trm ) is reduced by 100 mv resistance thresholds typical to cool resistance r typ_fall 13,200 16,500 19,800 cool to typical resistance r typ_rise 15,900 jeita warm temperature t jeita_ warm 45 c battery termination voltage (v trm ) is reduced by 100 mv resistance thresholds warm to typical resistance r warm_fall 5800 typical to warm resistance r warm_rise 4260 5200 6140 jeita hot temperature t jeita_hot 60 c no battery charging occurs resistance thresholds hot to warm resistance r hot_fall 3700 warm to hot resistance r hot_rise 2750 3350 3950 battery detection sink current i sink 13 20 34 ma source current i source 7 10 13 ma battery threshold low v batl 1.8 1.9 2.0 v high v bath 3.4 v battery detection timer t batok 333 ms timers clock oscillator frequency f clk 2.7 3 3.3 mhz start charging delay t start 1 s ec trickle charge t trk 60 min fast charge t chg 600 min charge complete t end 7.5 min v bat_sns = v trm , i chg < i end deglitch t dg 31 ms applies to v trk _dead , v rch , i end , v weak , v vin_ok _rise , and v vin_ok_fall watchdog 2 t wd 32 sec safety t safe 36 40 44 min battery short 2 t bat_shr 30 sec iled output pins voltage drop o ver iled v iled 200 mv i iled = 20 ma maximum operating voltage over iled v maxiled 5.5 v sys_en out put pin sys_en fet on resistance r on_sys_en 10 i sys_en = 20 ma
ADP5063 data sheet rev. 0 | page 6 of 44 parameter symbol min typ max unit test conditions/comments logic input pins maximum voltage on digital inputs v din_max 5.5 v applies to scl, sda, dig_io1, dig_io2, dig_io3 maximum logic low input voltage v il 0.5 v applies to scl, sda, dig_io1, dig_io2, dig_io3 minimum logic high input voltage v ih 1.2 v applies to scl, sda, dig_io1, dig_io2, dig_io3 pull - down resistance 215 350 610 k applies to dig_io1, dig_io2, dig_io3 1 undervoltage locko ut generated normally from iso_sx or iso_bx ; in certain transition cases , it can be generated from vinx . 2 these values are programmable via i 2 c. values are given with default register values. 3 the output current during charging may be limited by the input current limit or by the isothermal charging mode. 4 during weak charging mode, the charger provides at least 20 ma of charging current via the trickle charge branch to the batte ry unless trickle charging is disabled. any residual current that is not required by the system is also used to charge the battery . 5 either jeita1 (default) or jeita2 can be selected in i 2 c , or both jeita functions can be enabled or disabled in i 2 c. recommended input an d output capacitance s table 2. parameter symbol min typ max unit test conditions/comments capacitances effective capacitance vinx c vin x 4 10 f cbp c c bp 60 100 140 nf iso_sx c iso_s x 10 22 100 f iso_bx c iso_b x 10 22 f i 2 c - compatible interface timing specifications table 3. parameter 1 symbol min typ max unit i 2 c- compatible interface 2 capacitive load for each bus line c s 400 pf scl clock frequency f scl 400 khz scl high time t high 0.6 s scl low time t low 1.3 s data setup time t su, dat 100 ns data hold time t hd, dat 0 0.9 s setup time for repeated start t su, sta 0.6 s hold time for start/repeated start t hd, sta 0.6 s bus free time between a stop and a start condition t buf 1.3 s setup time for stop condition t su, sto 0.6 s rise time of scl/sda t r 20 300 ns fall time of scl/sda t f 20 300 ns pulse width of suppressed spike t sp 0 50 ns 1 guaranteed by design. 2 a master device must provide a hold time of at least 300 ns for the sda signal to bridge the undefined region of the falling edge of scl (see figure 2 ) .
data sheet ADP5063 rev. 0 | page 7 of 44 timing diagram figure 2 . i 2 c timing diagram sda s = start condition sr = repeated start condition p = stop condition scl s sr p s t low t su, dat t hd, sta t su, sto t hd, dat t su, sta t high t r t f t r t f t sp t buf 1 1593-002
ADP5063 data sheet rev. 0 | page 8 of 44 absolute maximum rat ings table 4. parameter rating vin1, vin2, vin3 to agnd C 0.5 v to +20 v all other pins to agnd C 0.3 v to +6 v continuous drain current, battery supple - mentary mode, from iso_bx to iso_sx 2.1 a storage temperature range C 65c to +150c operating junction temperature range C 40c to +125c soldering conditions jedec j - std -020 thermal resistance ja is specified for the worst - case conditions, that is, ja is specified for a device soldered in a circuit board for surface - mount packages. table 5. package type ja jc unit 20- lead lfcsp 35.6 3.65 c/w maximum power dissipation the maximum safe power dissipation in the ADP5063 package is limited by the associated rise in junction temperature (t j ) on the die. at a die temperature of approximately 150 c ( the glass transition temperature ) , the properties of the plastic change . even temporarily exceeding this temperature limit may change the stresses that the package exerts on the die, thereby perma - nently shifting the parametric performance of the ADP5063 . exceeding a junction temperature of 175 c for an extended period can result in changes in the silicon devices , potentially causing failure. esd caution s t r e s s es a b o ve t h o s e l i s t e d u n d e r a b s o l u t e m a x i m um r a t i n gs m a y c a u s e p e r m a n e n t dam a g e t o t h e d e v i c e . this is a s t r e s s r a t i n g o n l y ; fu n c t i o n a l o p e r a t i o n o f t h e d ev i c e a t t h e s e o r a n y o t h e r co n d i t i o ns a b o ve t h o s e indi c a t e d i n t h e o p e r a t i o na l s e c t i o n o f t h is s p e c i fi c a t ion is n o t i m p l i e d . e x p o su r e t o a b s o l u te ma x i m u m r a t in g c o n d i t i o n s fo r e x t e n d e d p e r i o d s m a y a ff e c t d e vi c e r e l i a b i l i t y .
data sheet ADP5063 rev. 0 | page 9 of 44 pin configuration an d function descripti ons figure 3 . pin configuration table 6 . pin function descriptions pin no. name type 1 description 1 scl i i 2 c- compatible interface serial clock. 2 dig_io3 gpio charging enable . when dig_io3 = low or high - z, charging is disabled. when dig_io3 = high, charging is enabled. 2 , 3 3 dig_io2 gpio set input current limit. when dig_io2 = low or high - z, the input limit is defined by dig_io1 setting. when dig_io2 = high, the input limit is 1500 ma. 2 , 3 4 bat_sns i battery voltage sense pin. 5 dig_io1 gpio set input current limit. this pin sets the input current limit directly. when dig_io 1 = low or high - z, the input limit is 100 ma. when dig_io1 = high, the input limit is 500 ma . 2 , 3 6, 7, 8 vin1, vin2, vin3 i/o power connections to usb vbus. these pins are high current inputs when in charging mode. 9, 10, 11 iso_s1, iso_s2, iso_s3 i/o linear charger supply side input to internal isolation fet /battery current regulation fet . h igh current input / output . 12, 13, 14 iso_b1, iso_b2, iso_b3 i/o battery supply side input to internal isolation fet /battery current regulation fet . 15 iled o open - drain output to indicator led. 16 sys_en o system enable. this pin is the battery ok flag/open - drain pull - down fet to enable the system when the battery reaches the v weak level. 17 sda i/o i 2 c- compatible interface serial data . 18 thr i battery pack thermistor connection. if this pin is not use d , connect a dummy 10 k resistor from thr to a gnd . 19 cbp i/o bypass capacitor i nput . 20 agnd g analog ground. n/a 4 ep n/a 4 exposed pad . connection of the exposed pad is not required. the exposed pad can be connected to analog ground to improve heat dissipation from the package to the board. 1 i is input, o is output, i/o is input/output, g is ground , and gpio i s the factory programmable general - purpose input/output. 2 see the digital input and output options section for details. 3 the dig_iox setting defines the in i tial state of the ADP5063 . if the parameter or the mode that is related to each dig_iox pin setting is changed ( by programming an equivalent i 2 c register bit or bits ) , the i 2 c register setting t akes precedence over the dig_iox pin setting. vinx connection or disconnection resets control to the dig_iox pin. 4 n/a = not applicable. 1 scl 2 dig_io3 3 dig_io2 4 bat_sns 5 dig_io1 13 iso_b2 14 iso_b3 15 iled 12 iso_b1 11 iso_s3 6 vin1 7 vin2 8 vin3 10 iso_s2 9 iso_s1 18 thr 19 cbp 20 agnd 17 sda 16 sys_en notes 1. connection of the exposed pad is not required. the exposed pad can be connected to analog ground to improve heat dissipation from the package to board. 1 1593-003 ADP5063 t o p view (not to scale)
ADP5063 data sheet rev. 0 | page 10 of 44 typical performance characteristics v vin x = 5.0 v, c vin x = 10 f, c iso_s x = 44 f, c iso_b x = 22 f, c c bp = 100 nf , all registers are at default values, unless otherwise noted. figure 4 . system voltage vs. system output current, ldo mode, vsystem [2:0] = 000 ( b inary) = 4.3 v figure 5 . system voltage vs. input voltage ( i n dropout), ldo mode, vsystem [2:0] = 000 ( b inary) = 4.3 v figure 6 . battery charge current vs. battery voltage, ichg [4:0] = 01001 (binary) = 500 ma, ilim [3:0] = 1111 (binary) = 2100 ma figure 7 . ideal diode r on vs. battery voltage, i iso_s x = 500 ma, vin x o pen 0.01 0.1 1 system voltage (v) system output current (a) 4.20 4.22 4.24 4.26 4.28 4.30 4.32 4.34 4.36 4.38 4.40 1 1593-004 3.5 3.6 3.7 3.8 3.9 4.0 4.1 4.2 4.3 4.4 4.5 4.0 4.4 4.8 5.2 5.6 6.0 6.4 6.8 system voltage (v) input voltage (v) load = 100ma load = 500ma load = 1000ma 1 1593-005 charge current (ma) b a tte r y vo lt age (v) weak charge fast charge trickle charge 1 1593-009 0 100 200 300 400 500 600 700 800 900 1000 1.8 2.3 2.8 3.3 3.8 40 45 50 55 60 65 70 isolation fet resistance (m?) battery voltage (v) 1 1593-010 2.7 2.9 3.1 3.3 3.5 3.7
data sheet ADP5063 rev. 0 | page 11 of 44 figure 8 . input current vs. input voltage , v iso_bx = 3.3 v figure 9 . ideal diode r on vs. load current, v iso_bx = 3.6 v figure 10 . charge profile, ilim[3:0] = 0110 (binary) = 50 0 ma, lifepo 4 battery capacity = 500 mah 1 1593-0 1 1 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 2 3 4 5 6 7 8 input current (ma) input vo lt age (v) d e f a u l t s t a r t u p d i s _ l d o = h i g h 40 70 65 60 55 50 45 0 0.5 1.0 1.5 2.0 isolation fet resistance (m?) load current (a) 1 1593-012 0 0.1 0.2 0.3 0.4 0.5 0.6 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 0 20 40 60 80 charge current (a) battery voltage (v) charge time (minutes) v bat_sns i iso_b 1 1593-013
ADP5063 data sheet rev. 0 | page 12 of 44 temperature characte ristics figure 11 . battery leakage (standby) current vs . amb ient temperature , standby mode figure 12 . vinx quiescent current vs. amb ient temperature , dis_ ldo = h igh figure 13 . system voltage accuracy vs. ambient temperature, load = 100 ma, v vinx = 5.5 v figure 14 . system voltage accuracy vs. ambient te mperature, trickle charge mode, v iso_sx = 4.3 v and v vinx = 5.0 v, or v iso_sx = 5.0 v and v vinx = 6.0 v figure 15 . vinx q uiescent current vs. amb ient temperature , ldo mode figure 16 . termination (v trm ) voltage accuracy vs. ambient temperature 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 ?40 ?15 10 35 60 85 s t andb y current (a) ambient temper a ture (c) v iso_bx = 3.6v v iso_bx = 4.2v v iso_bx = 5.5v 1 1593-014 ?40 ?25 ?10 5 20 35 50 65 80 95 1 10 125 ambient temper a ture ( c ) 1 1593-015 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 vinx quiescent current (ma) ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 0.5 ?40 ?25 ?10 5 20 35 50 65 80 95 110 125 system voltage accuracy (%) ambient temperature (c) v iso_sx = 4.3v v iso_sx = 5.0v 1 1593-016 ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 0.5 ?40 ?25 ?10 5 20 35 50 65 80 95 1 10 125 system vo lt age accurac y (%) ambient temper a ture ( c ) v iso_sx = 4.3v v iso_sx = 5.0v 1 1593-017 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 ?40 ?25 ?10 5 20 35 50 65 80 95 1 10 125 vinx quiescent current (ma) ambient temper a ture (c) v in = 4.0v v in = 5.0v v in = 6.7v 1 1593-018 ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 0.5 ?40 ?25 ?10 5 20 35 50 65 80 95 1 10 125 v trm vo lt age accurac y (%) ambient temper a ture (c) v trm = 3.5v v trm = 3.8v v trm = 4.2v 1 1593-019
data sheet ADP5063 rev. 0 | page 13 of 44 figure 17 . fast charge current cc mode vs. ambient temperature figure 18 . vinx overv oltage threshold vs. ambient temperature figure 19 . input current limit vs . ambient temperature 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 ?40 ?15 10 35 60 85 110 charge current (a) ambient temper a ture ( c ) i chg = 750ma i chg = 500ma i chg = 1300ma 1 1593-020 ambient temper a ture (c) 6.80 6.85 6.90 6.95 7.00 ?40 ?25 ?10 5 20 35 50 65 80 95 1 10 125 vinx ove r volt age threshold (v) 1 1593-021 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 ?40 ?25 ?10 5 20 35 50 65 80 95 1 10 125 input current limit (a) ambient temper a ture (c) i lim = 1500ma i lim = 900ma i lim = 500ma i lim = 100ma 1 1593-022
ADP5063 data sheet rev. 0 | page 14 of 44 typical waveforms figure 20 . charging startup , v vinx = 5.0 v, ilim [3:0] = 0110 (binary) = 500 ma, ichg [4:0] = 01110 (binary) = 750 ma figure 21 . load transient, i i so_sx l oad = 300 ma to 1500 ma to 300 ma figure 22 . i nput current - limit transition from 100 ma to 900 ma, iso_sx l oad = 66 ?, charging = 750 ma figure 23 . usb vbus disconnect ion figure 24 . load transient , i iso_sx l oad = 300 ma to 1500 ma to 300 ma, en_chg = h igh, ilim [3:0] = 0110 (binary) = 500 ma figure 25 . battery detection waveform , vsystem[2:0] = 000 (binary) = 4.3 v, no battery i vinx i iso_bx v vinx v iso_sx ch1 2.00v ch2 200ma ch3 200ma ch4 2.00v m1.00ms a ch2 120ma 1 2 3 4 t 1.00ms t 1 1593-023 i iso_sx v iso_sx ch1 100mv ch2 500ma m1.00ms a ch2 820ma 1 2 t 3.00ms t 1 1593-024 i iso_bx v iso_sx v vinx i vinx ch1 200mv ch2 200mv ch3 500ma ch4 500ma m40.0s a ch3 610ma 1 2 3 4 t 0.00s t 1 1593-025 i vinx i iso_bx v vinx v iso_sx ch1 2.00v ch2 200ma ch3 200ma ch4 2.00v m200.0s a ch2 216ma 1 2 3 4 t 0.00s t 1 1593-026 3 i iso_sx i iso_bx v iso_sx ch1 1.00v ch2 500ma ch3 500ma m1.0ms a ch2 ?610ma 1 2 t 3.00ms t 1 1593-027 i iso_bx v iso_bx ch2 2.00v ch3 10.0ma m200ms a ch3 17.2ma 2 3 t 0.00s t 1 1593-028
data sheet ADP5063 rev. 0 | page 15 of 44 theory of operation summary of operation modes table 7 . summary of operation modes mode name v vinx c ondition battery c ondition trickle c harge ldo fet s tate battery i solation fet system v oltage iso_sx additional conditions 1 ic off, standby 0 v any battery condition off off on battery voltage or 0 v ic off, suspend 5 v any battery condition off off on b attery voltage dis_ldo = high ldo mode off, isolation fet on 5 v any battery condition off off on battery voltage disable ldo and enable isolation fet ldo mode off, isolation fet off (system off) 5 v any battery condition off off off 0 v enable battery charging ldo mode, charger off 5 v any battery condition o ff ldo o ff 4.3 v enable battery charging trickle charge mode 5 v battery < v trk_dead on ldo off 4.3 v enable battery charging weak charge mode 5 v v trk_dead b attery < v weak o n chg chg 3. 4 v enable battery charging fast charge mode 5 v battery v weak o ff chg chg 3. 4 v (min imum ) enable battery charging charge mode, no battery 5 v open off ldo off 4.3 v enable battery charging charge mode, battery (iso_bx) shor ted 5 v short ed on ldo off 4.3 v enable battery charging 1 see table 8 for details. table 8 . operation mode controls pin c onfiguration dig_iox equivalent i 2 c a ddress, d ata bit (s) description enable battery charging dig_io3 0x07, d0 low = all charging modes disabled (fast, weak, trickle) . high = all charging modes enabled (fast, weak, trickle) . disable ldo and enable isolation fet not applicable 0x07, d3, d0 low = ldo enabled. high = ldo disabled . in addition, when en_chg = low, the battery isolation fet is on; when en_chg = high, the battery isolation fet is off.
ADP5063 data sheet rev. 0 | page 16 of 44 introduction the ADP5063 is a fully programmable i 2 c charger for single cell lithium ion or lithium polymer batteries , suitable for a wide range of portable applications. the linear charger architecture enables up to 2.1 a output current at 4.3 v to 5.0 v (i 2 c programmable ) on the system power supply , and up to 1.3 a of charge current into the battery from a dedicated charger. the ADP5063 operates from a n input voltage of 4 v up to 6.7 v but is tolerant of voltages of up to 20 v. the 20 v voltage tolerance alleviates the concerns of the usb bus spiking during discon - nection or connection scenarios. the ADP5063 features an internal fet between the linear charger output and the battery. this feature permits battery isolation and, therefore , system powering under a dead battery or no battery scenar io, which allows immediate system function up on connection to a usb power supply. the ADP5063 is fully compliant with usb 3.0 and the usb battery charging 1.2 compliance plan specification . the ADP5063 is chargeable via the mini usb vbus pin from a wall charger, car charger, or usb host port. based on the type of usb source, which is detected by an external usb detection device, the ADP5063 can be set to apply the correct current limit for optimal charging and usb compliance. the usb charger permits correct oper - ation under all usb compliant sources such as wall chargers, hos t chargers, hub chargers, and standard host and hubs. a processor can control the usb charger using the i 2 c interface to program the charging current and numerous other parameters , including ? trickle charge current level ? t rickle charge voltage threshold ? weak charge (constan t current) current level ? fast charge (constan t current) current level ? fast charge (constant voltage) voltage level ? fast charge safety timer period ? w atchdog safety timer parameters ? weak battery thr eshold detection ? charg ing complete thre shold ? recharge threshold ? charg ing enable/disable ? battery pack temperature detection and automatic charger shutdown
data sheet ADP5063 rev. 0 | page 17 of 44 figure 26 . block diagra m 6 7 9 10 iso_s1 iso_s2 iso_s3 vin1 vin2 11 14 iso_b2 18 thr + ? 0.5v ntc current control cold cool warm hot ntc trickle current source 19 battery detection sink 4 bat_sns battery detection battery: open short trickle weak cv mode recharge charge control eoc to system load + ? 6.85v 3.9v + ? + ? vin overvoltage vin limit battery isolation fet vin good battery overvoltage 1 17 scl sda to usb vbus or wall adapter 20 agnd 5 3 2 dig_io1 dig_io2 dig_io3 16 sys_en 3mhz osc single cell li-ion tsd 140c sys_en output logic thermal control 8 vin3 cbp iso_b3 13 12 15 iled iled output logic high voltage blocking ldo fet + ? ldo fet control 3.4v i 2 c interface and control logic vin ? 150mv iso_b1 1.9v warning 130c isothermal 115c tsd down 110c 1 1593-029
ADP5063 data sheet rev. 0 | page 18 of 44 the ADP5063 includes a number of significant features to optimiz e charging and functionality , including ? thermal reg ulation for maximum performance . ? usb h ost current limit s. ? te rmination voltage accuracy: 1 .7 % . ? battery thermistor input with automatic charger shutdown in the event that the battery temperature exceeds li mits ( c ompliant with the jeita li - ion battery cha rging temperature specification ) . ? three external pins (dig_io1, dig_io2 , and dig_io3) that directly control a number of parameters. these pins are factory programmable for maximum flexibility. they can be factory programmed for functions such as ? enable/disable charging . ? control of the 100 ma or 500 ma input current limit . ? cont rol of the 1500 ma input current limit . ? control of the battery charge current . ? an i nterrupt output pin . see the digital input and output options section for details . charger modes input current limit the vinx input current limit is controlled via the internal i 2 c ilim bits . the input current limit can also be controlled via the dig_io1 pin (if factory programmed to do so) as outlined in table 9 . any change from the 100 ma i 2 c default takes precedence over the pin setting. table 9 . dig_io1 o peration dig_io1 function 0 100 ma input current limit or i 2 c programmed value 1 500 ma input current limit or i 2 c programmed value (or reprogrammed i 2 c value from 100 ma default) usb compatibility the ADP5063 features a n i 2 c - programmable input current limit to ensure compatibility with the requirements listed in table 10 . the current limit defaults to 100 ma to allow com - patibility with a usb host or hub that is not configured. the i 2 c register default is 100 ma. an i 2 c write command to the ilim bits override s the dig_iox pins , and the i 2 c register default value can be reprogrammed for alternative requirements. when the input current - limit feature is used, the available input current may be too low for the charger to meet the programmed charging current , i chg , thereby reducing the rate of charge and setting the vin_i li m flag. when connecting voltage to vinx without the proper voltage level on the battery side, the high voltage blocking mechanism is in a state wherein it draws a current of < 1 ma until v vi n x rea che s the vin_ok level. the ADP5063 charger provides support for the following con - nections through the single connector vinx pin, as shown in table 10. table 10. input current compatibility with standard usb l imits mode standard usb limit ADP5063 function usb (china only) 100 ma limit for stan dard usb host or hub 100 ma input current limit or i 2 c programmed value 300 ma limit for chinese usb specification 300 ma input current limit or i 2 c programmed value usb 2.0 100 ma limit for stan dard usb host or hub 100 ma input current limit or i 2 c programmed value 500 ma limit for stan dard usb host or hub 500 ma input current limit or i 2 c programmed value usb 3.0 150 ma limit for super speed usb 3.0 host or hub 150 ma input current limit or i 2 c programmed value 900 ma limit for super speed, high speed usb host or hub charger 900 ma input current limit or i 2 c programmed value dedicated charger 1500 ma limit for dedicated charger or low/full speed usb host or hub charger 1500 ma input current limit or i 2 c programmed value
data sheet ADP5063 rev. 0 | page 19 of 44 trickle charge mode a deeply discharged li - ion cell can exhibit a very low cell voltage , making it unsafe to charge the cell at high current rates. the ADP5063 charger uses a trickle charge mode to reset the battery pack protection circuit and lift the cell voltage to a safe level for fast charging. a cell with a voltage below v trk_dead is charge d with the trickle mode current, i trk_dead . during trickle charging mode, the charger_status [2:0] bits are set. during trickle charging , the iso_sx node is regulated to v iso_strk by the ldo and the battery isolation fet is off, which means that the battery is isolated from the system power supply. trickle charge mode timer the duration of trickle charge mode is monitored to ensure that the battery is revived from its deeply discharged state. if trickle charge mode runs for longer than 60 minutes without the cell voltage reaching v trk_dead , a fault condition is assumed and charging stops. the fault condition is asserted on the charger_status [2:0] bits , allowing the user to initiate the fault recovery procedure specified in the fault recovery section. weak charge mode (constant current) when the battery voltage exceeds v trk_dead but is less than v weak , the charger switches to intermediate charge mode. during the weak charge mode, the battery voltage is too low to allow the full system to power up. because of the low battery level, the usb transceiver cannot be powered and, therefore, cannot enumerate fo r more current from a usb host. conse - quently, the usb limit remains at 100 ma. the system microcontroller may or may not be powered by the charger output voltage (v iso_sfc ) , depending upon the amount of current that the microcontroller and/or the system a rchitecture requires . when the iso_s x pins power the microcontroller , the battery c harge current (i chg_weak ) cannot be increased above 20 ma to ensure microcontroller operat ion (if doing so) , nor can i chg_weak be increased above the 100 ma usb limit. there - fore , set the battery charging current as follows: ? set the default 20 ma via the linear trickle charger branch (to ensure that the microprocessor remains alive if powered b y the main charger outpu t, iso_sx). any residual current on the main charger output, iso_sx, is used to charge the battery. ? during weak current mode, other features may prevent the weak charging current from reaching its full programmed value. isothermal charging mode or input current limiting for usb compatibility can affect the p rogrammed weak charging current value under certain operating conditions. during weak charging, the iso_sx node is regulated to v iso_sfc by the battery isolation fet. fast charge mode (constant current) when the battery voltage exceeds v trk_dead and v wea k , the charger switches to fast charge mode, charging the battery with the constant current, i chg . during fast charge mode (constant current), the charger_status [2:0] bits are set to 010 . during constant current mode, other features may prevent the current, i chg , from reaching its full programmed value. isothermal charging mode or input current limiting for usb compatibility can affect the value of i chg under certain oper ating conditions. the voltage on iso_sx is regulated to stay at v iso_sfc by the battery isolation fet when v iso_bx < v iso_sfc . fast charge mode (constant voltage) as the battery charges, its voltage rises and approaches the termi - nation voltage, v trm . the ADP5063 charger mo nitors the voltage on the bat_sns pin to determine when charging should end. however, the internal esr of the battery pack combined with the printed circuit board ( pcb ) and other parasitic series resis - tances creat es a voltage drop between the sense point at the bat_sns pin and the cell terminal. to compensate for this and to ensure a fully charged cell, the ADP5063 enters a constant voltage charging mode when the termination voltage is detected on the bat_sns pin. the ADP5063 reduces charge current gradually as the cell continues to charge, maintaining a voltage of v trm on the bat_sns pin. duri ng fast charge mode (constant voltage), the charger_ status bits are set to 011 . fast charge mode timer the duration of fast charge mode is monitored to ensure that the battery is charging correctly. if the fast charge mode runs for longer than t chg without the voltage at the bat_sns pin reaching v trm , a fault condition is assumed and charging stops. the fault condition is asserted on the charger_status [2:0] bits, allowing the user to initiate the fault recovery procedure as specified in the fault recovery section. if the fast charge mode runs for longer than t chg , and v trm has been reached on the bat_sns pin but the charge current has not yet fal len below i end , charging stops. no fault condi tion is asserted in this circumstance , and charging resumes as normal if the recharge threshold is breached. watchdog timer the ADP5063 charger features a programmable watchdog timer function to ensure that charging is under the control of the pro - cessor. the watchdog timer starts running when the ADP5063 charger determines tha t the processor should be operational, that is, when the processor sets the reset_wd bit for the first time or when the battery voltage is greater than the weak battery threshold, v weak . when the watchdog timer has been triggered, it must be reset regularl y within the watchdog timer period, t wd . while in charger mode, i f the watchdog timer expires without being reset, the ADP5063 charger assumes that there is a software problem and triggers the safety timer, t safe . for more infor mation see the safety timer section.
ADP5063 data sheet rev. 0 | page 20 of 44 safety timer while in charger mode, i f the watchdog timer expires , the ADP5063 charger initiates the safety timer, t safe (see the watchdo g ti me r section ). if the processor has pr ogrammed charging parameters by the time the ch arger in i tiates the safety timer , i lim is set to the default value. charging continues for a period of t safe , a nd then the charger switches off and sets the charger_status [2:0] bits . charge complete the ADP5063 charger monitor s the charging current while in fast charge constant voltage mode. if the current falls below i end and remains below i end for t end , charging stops and the chdone flag is set. if the charging current falls below i end for less than t end and then rises above i end again, the t end timer resets. recharge after the detection of charge co mplete and the cessation of charging, the ADP5063 charger monitors the bat_sns pin as the battery discharges through normal use. if the bat_sns pin voltage falls to v rch , the charger reactivat es charging. under most circumstances, triggering the recharge threshold results in th e charger starting directly in fast charge constant voltage mode. the recharge function can be disabled in the i 2 c interface , but a status bit ( r egister address 0x0c , b it 3) inform s the system that a recharge cycle is required. ic enable/disable the ADP5063 ic can be disabled by the dig_io2 digita l input pin (if factory programmed to do so) o r by the i 2 c registers. all internal control circuits are disab led when the ic is disabled. dis - abling the ic1 option can also control the state s of the ldo fet and the battery isolation fet. it is critical to note that during the disable ic1 mode, a high voltage at vinx pass es to the i nternal supply voltage because all of the internal control circuits are disabled. the vinx supply voltage must fulfill the following condition : v iso_bx < vinx < 5.5 v battery charging enable/disable the ADP5063 c harging function can be disabled by setting the i 2 c en_chg bit to low . the ldo to the system still operates under this circumstance and can be set in i 2 c to the default or i 2 c programmed s ystem voltage from 4.3 v to 5.0 v (see table 26 for details). the ADP5063 c harging function can also be controlled via one of the external dig_iox pins (if factory programmed to do so). any change in the i 2 c en_chg bit takes precedence over the pin setting. battery voltage limit to prevent charging the battery monitor of the ADP5063 charger can be configured to m onitor batte ry voltage and prevent charging when the battery voltage is higher than v chg_vlim ( typically 3. 2 v) during charging start - up (enabled by en_chg or dig_io3). this function can prevent unnecessary charging of a half discharged battery and, as suc h, can extend the lifetime of the li - ion battery cell. charging start s automatically when the battery voltage drops below v chg_vlim and continues through full charge cycle until the battery voltage reaches v trm ( typically 3.6 v). by default , the charging voltage limit is disabled , and it can be enabled via i 2 c r egister address 0x08, b it 5 ( en_chg_vlim ) . sys_en output the ADP5063 features a sys_en open - drain fet to enable the system until the battery is at the minimum required le vel for guaranteed system start up. when there are minimum battery voltage and/or minimum battery charge level requirements, the operatio n of sys_en can be set by i 2 c programming. the sys_en operation c an be factory prog rammed to four different operating conditions , as described in table 11 . table 11 . sys_en m ode d escriptions sys_en mode selection description 00 sys_en is activated when ldo is active and system voltage is available . 01 sys_en is activated by the iso_bx voltage , the b attery charging mode . 10 sys_en is activated and the i solation fet is disabled when the battery drops below v weak . this o ption is active when vinx = 0 v and the battery monitor is act ivated from register 0x07, bit 5 (en_bmon). 11 sys_en is active in ldo mode when the charger is disabled. sys_en is active in charging mode when v iso_bx v weak . indicator led output (iled) the iled is an open - drain output for an indicator led connec - tion. optionally , the iled output can be used as a status output for a microcontroller. indicator led modes are listed in table 12 . table 12 . in dicator led operation m odes ADP5063 mode iled m ode on/ off t ime ic o ff off ldo mode off off ldo mode on off charge m ode continuously on timer e rror (t trk , t chg , t safe ) blinking 167 ms/ 833 ms overt emperature (t sd ) blinking 1 sec/ 1 sec
data sheet ADP5063 rev. 0 | page 21 of 44 thermal management isothermal charging the ADP5063 includes a thermal feedback loop that limits the charge current when the die temperature exceeds t lim (typically 115 c). as the on - chip power dissipation and die temperature increase, the charge current is automatically reduced to maintain the die temperature within the recommended range. as the die temperature decreases due to lower on - chip power dissipation or ambient temperature , the charge current returns to the pro - grammed level. d uring isothermal charging, the therm_lim i 2 c flag is se t to high. this thermal feedback control loop allows the user to set the programmed charge current based on typical rathe r than worst - case conditions. the ADP5063 does not include a thermal fee d back loop to limit iso_sx load current in ldo mode. if the power dissipated on chip during ldo mode causes th e die temperature to exceed 130c, an interrupt is generated. if the die temperature continues to rise beyond 140 c, the device enter s thermal shu tdown. thermal shutdown and thermal early warning the ADP5063 charger features a thermal shutdown threshold detector. if the die temperature exceeds t sd , the ADP5063 charger is disabled, and the tsd 140 c bit is set. the ADP5063 charger can be reenabled when the die temperature drops below t he t sd falling limit and the tsd 140c bit is reset. to reset the tsd 140c bit, write to the i 2 c f ault register, register address 0x0d (bit 0) or cycle the power. before the die temperature reaches t sd , the early warning bit is set if t sdl is exceeded. th is allows the system to accommodate power consumption before thermal shutdown occurs. fault recovery before performing the following operation, i t is important to ensure that the cause of the fault has been rectified. to recover from a charger fault (when charger_status [2:0] = 110), cy cle the power on vinx or write high to reset the i 2 c fault bits in the fault register (register address 0x0d) . battery isolation fe t the ADP5063 charger features an integrated battery isolation fet for power path control. the battery isolation fet isolates a deeply discharged li - ion cell from the system power supply in both trickle and fast charge modes, thereby allowing the system to be powered a t all times. when vinx is below v vin_ok_rise , the battery isolation fet is in full conducting mode. the battery isolation fet is off during trickle charge mode. when the battery voltage exceeds v trk _dead , the battery isolation fet switches to the system volt age regulation mode. during system voltage regulation mode, the battery isolation fet maintains the v iso_sfc voltage on the iso_sx pins. when the battery voltage exceeds v iso_sfc , the battery isolation fet is in full conducting mode. the battery isola tion fet supplements the battery to support high current functions on the system power supply. when the voltage on iso_sx drops below v iso_bx , the battery isolation fet enters into full conducting mode. when voltage on iso_sx rises above v iso_bx , the isola tion fet enters regulating mode or full conduction mode, depending on the li - ion cell voltage and the linear charger mode. battery detection battery voltage level detection the ADP5063 c harger features a battery detection mechanism to detect an absent battery. the charger actively sinks and sources current into the iso_bx node, and voltage vs. time is detected. the sink phase is used to detect a charged battery, wh ereas the source phase is used to detect a discharged batter y. the sink phase (see figure 27 ) sinks i sink current from the iso_bx pins for a time period , t batok . if iso_bx is below v batl w hen the t batok timer expires, the charger assumes that no battery is present and starts the source phase. if the iso_bx pin exceeds the v batl voltage when the t batok timer expires, the charger assumes that the battery is present and begins a new charge cycle. the source phase sources i source curren t to the iso_bx pin s for a time period , t batok . if iso_bx exceeds v bath before the t batok timer expires, the charger assumes that no battery is present. if the iso_bx pin does not exceed the v bath voltage when the t batok timer expires, the charger assumes that a battery is present and begins a new charge cycle.
ADP5063 data sheet rev. 0 | page 22 of 44 figure 27 . sink phase figure 28 . trickle charge battery (iso_bx) s hort d etection a battery short occurs under a damaged battery condition or when the battery protection circuitry is enabled. on commencing trickle char ging, the ADP5063 charger moni - tors the battery voltage. if this battery voltage does not exceed v bat_shr within the specified timeout period, t bat_shr , a fault is declared and the charger is stopped by tur ning the battery isolation fet off , but the system voltage is maintained at v iso_strk by the linear regulator. after source phase, if the iso_bx or bat_sns level remains below v bath , either the battery voltage is low or the battery node is shorted. becaus e the battery voltage is low, trickle charging mode is initiated (see figure 28 ). if the bat_sns level remains below v bat_shr after t bat_shr has elapsed, the ADP5063 assumes that the battery node is shorted. the trickle charg e branch is active during the battery short scenario, and trickle charge current to the battery is maintained until the 60 - minute tr ickle charge mode timer expires . battery pack tempera ture sensing battery thermistor input the ADP5063 c harger features battery pack temperature sensing that precludes charging when the battery pack temperature is outside the specified range. the thr pin provides an on a nd off switching current source that must be connected directly to the battery pack thermistor terminal. the activation interval of the thr current source is 167 ms. the battery pack temperature sensing can be controlled by i 2 c, using the conditions shown in t able 13 . note that the i 2 c register default setting for en_thr (register address 0x07) is 0 = temperature sensing off. table 13 . thr input function conditions thr f unction vinx v iso_bx open or v in = 0 v to 4.0 v <2.5 v off open or v in = 0 v to 4.0 v >2.5 v off, controlled by i 2 c 4 v to 6.7 v don't care always on if the battery pack thermistor is not connected directly to the thr pin, a 10 k? (tolerance 20%) dummy resistor must be connected between the thr input and a gnd . leaving the thr pin open results in a false detection of the battery temperature being <0c , and charging is disabled. the ADP5063 charger monitors the voltage in the thr pin and suspends charging when the current is outside the range of less than 0c or greater than 60c. the ADP5063 charger is designed for use with an ntc thermistor in the battery p ack with a nominal room tempera ture value of either 10 k? at 25c or 100 k? at 25c, which is selected by factory programming . t he ADP5063 charger is designed for use with an ntc thermistor in the battery pack with a temperatur e coefficient curve (beta). factory programming supports eight beta values covering a range fro m 3150 to 4400 (see table 43). open iso_bx sink phase logic status open or short t batok v batl i sink iso_bx open open logic status source phase t batok v ba t h i source 1 1593-030 i source short sink phase source phase trickle charge iso_bx s h o r t iso_bx short i s o _b x logi c s t a t u s o pen o r s h o r t t batok logi c s t a t u s s h o r t o r lo w ba tt e r y t batok logi c s t a t u s s h o r t t bat_shr v batl v bath v bat_shr i trk_dead i sink 1 1593-031
data sheet ADP5063 rev. 0 | page 23 of 44 jeita li - ion battery temperature charging specification the ADP5063 is compliant with the jeita1 and jeita2 li - ion battery charging temperature specifications as outlined in table 14 and table 16, respectively. jeita function can be enabled via the i 2 c interface and , optionally , the jeita1 or jeita2 function can be selected via the i 2 c interface . alternatively , the jeita1 or jeita2 function can be enabled as the default setting by factory programming. when the ADP5063 identifies a hot or cold battery condition, the ADP5063 takes the following actions: ? stops charging the battery. ? connects or enables t he battery isolation fet such that the ADP5063 continues in ldo mode. table 14 . jeita1 s pecifications parameter symbol conditions min max unit jeita1 cold temperature limits i jeita_cold no battery charging occurs . 0 c jeita1 cool temperature limits i jeita_cool battery charging occurs at approx imately 50% of the programmed level . s ee table 15 for specific charging current reduction levels . 0 10 c jeita1 typical temperature limits i jeita_typ normal battery charging occurs at the default/programmed levels . 10 45 c jeita1 warm temperature limits i jeita_warm battery termination voltage (v trm ) is reduced by 100 mv from the programmed value . 45 60 c jeita1 hot temperature limits i jeita_hot no battery charging occurs . 60 c table 15 . jeita1 reduced charge current levels, battery cool temperature ichg[4:0] default ichg jeita1 00000 = 50 ma 50 ma 00001 = 100 ma 50 ma 00010 = 150 ma 50 ma 00011 = 200 ma 100 ma 00100 = 250 ma 100 ma 00101 = 300 ma 150 ma 00110 = 350 ma 150 ma 00111 = 400 ma 200 ma 01000 = 450 ma 200 ma 01001 = 500 ma 250 ma 01010 = 550 ma 250 ma 01011 = 600 ma 300 ma 01100 = 650 ma 300 ma 01101 = 700 ma 350 ma 01110 = 750 ma 350 ma 01111 = 800 ma 400 ma 10000 = 850 ma 400 ma 10001 = 900 ma 450 ma 10010 = 950 ma 450 ma 10011 = 1000 ma 500 ma 10100 = 1050 ma 500 ma 10101 = 1100 ma 550 ma 10110 = 1200 ma 600 ma 10111 to 11 111 = 130 0 ma 650 ma table 16 . jeita2 specifications parameter symbol conditions min max unit jeita2 cold temperature limits i jeita_cold no battery charging occurs . 0 c jeita2 cool temperature limits i jeita_cool battery termination voltage (v trm ) is reduced by 100 mv from the programmed value . 0 10 c jeita2 typical temperature limits i jeita_typ normal battery charging occurs at the default/programmed levels . 10 45 c jeita2 warm temperature limits i jeita_warm battery termination voltage (v trm ) is reduced by 100 mv from the programmed value . 45 60 c jeita2 hot temperature limits i jeita_hot no battery charging occurs . 60 c
ADP5063 data sheet rev. 0 | page 24 of 44 figure 29 . simplified battery and vin x connect flowchart reset all registers power-on reset vin_ok = high no no no no no ic off enable ldo to charging mode enable charger low battery chg ldo mode system off yes yes yes yes yes yes no enable charger v bat_sns < v chg_vlim 1 1593-032
data sheet ADP5063 rev. 0 | page 25 of 44 figure 30 . simplified charging mode flowchart to charging mode i vinx < i lim temp < t lim yes no no charge complete yes t wd expired yes no trickle charge yes timer fault or bad battery yes no no v bat_sns < v trk yes no yes no no vin_ok = high vin_ok = high yes yes t start expired power-down no no no yes yes 1 no no yes yes run battery detection fast charge no yes to ic off v bat_sns = v rch t wd expired t safe or t trk expired i out < i end v bat_sns < v trk watchdog expired start t safe i bus = 100ma vin_ilim = high i vinx = i lim run battery detection therm_lim = high temp = t lim t safe or t chg expired watchdog expired start t safe i bus = 100 ma timer fault or bad battery 1 see timer specs v bat_sns = v trm cc mode charging cv mode charging 1 1593-033
ADP5063 data sheet rev. 0 | page 26 of 44 i 2 c interface the ADP5063 includes an i 2 c - compatible serial interface for control of the charging and ldo functions, as well as for a readback of the system status registers. the i 2 c chip address is 0x28 in write m ode and 0x29 in read mode. register values are reset to the default values when the vinx supply falls below the falling voltage threshold , v vin_ok_fall . the i 2 c registers also reset when the battery is disconnected and v in is 0 v. the subaddress content selects which of the ADP5063 registers is written to first. the ADP5063 sends an acknowledgement to the master after the 8 - bit data byte has been written (see figure 31 for an example of the i 2 c write sequence to a single register) . the ADP5063 increments the subaddress automatically and starts receiving a data byte at the next register until the master sends an i 2 c stop , as shown in figure 32. figure 33 shows the i 2 c read sequence of a single register. ADP5063 sends the data from the register denoted by the subaddress and increments the subaddress automatically, sending data from the next register until the master sends an i 2 c stop condition , as shown in figure 34. figure 31 . i 2 c single register write sequence figure 32 . i 2 c multiple register write sequence figure 33 . i 2 c single register read sequence figure 34 . i 2 c multiple register read sequence subaddress chip address st 0 0 1 0 1 0 0 0 0 0 sp ADP5063 receives data 0 = write 0 master stop ADP5063 ack ADP5063 ack ADP5063 ack 1 1593-034 0 = write chip address st 0 0 1 0 1 0 0 0 0 0 sp ADP5063 receives data to register n 0 master stop 0 ADP5063 receives data to register n + 1 0 ADP5063 receives data to last register ADP5063 ack ADP5063 ack ADP5063 ack ADP5063 ack ADP5063 ack subaddress register n 1 1593-035 st st sp 0 = write subaddress chip address 0 0 1 0 1 0 0 0 0 1 0 master stop chip address ADP5063 sends data 0 0 1 0 1 0 0 0 1 = read 1 0 ADP5063 ack ADP5063 ack ADP5063 ack master ack 1 1593-036 st st sp 0 = write master stop 1 = read subaddress register n chip address 0 0 1 0 1 0 0 0 0 0 ADP5063 sends data of register n 0 master ack 0 ADP5063 sends data of register n + 1 master ack 1 ADP5063 sends data of last register master ack chip address 0 0 1 0 1 0 0 0 1 0 ADP5063 ack ADP5063 ack ADP5063 ack 1 1593-037
data sheet ADP5063 rev. 0 | page 27 of 44 i 2 c register map see the factory-programmable options section for programming option details. note that a blank cell indicates a bit that is not used or is reserved for future use. table 17. i 2 c register map register d7 d6 d5 d4 d3 d2 d1 d0 addr. name 0x00 manufac- turer and model id manuf[3:0] model[3:0] 0x01 silicon revision rev[3:0] 0x02 vinx pin settings ilim[3:0] 1 0x03 termination settings vtrm[5:0] 1, 2 chg_vlim[1:0] 1, 2 0x04 charging current settings ichg[4:0] 1, 2 itrk_dead[1:0] 1 0x05 voltage thresholds dis_rch 1, 3 vrch[1:0] 1 vtrk_dead[1:0] 1, 3 vweak[2:0] 1 0x06 timer settings en_tend 1 en_chg_timer 1 chg_tmr_period 1 en_wd 1, 3 wd_period 1 reset_wd 0x07 functional settings 1 dis_ic1 1 en_bmon 1 en_thr 1 dis_ldo 1 en_eoc 1 en_chg 1 0x08 functional settings 2 en_jeita 1, 3 jeita_select 1, 3 en_chg_vlim 1, 3 ideal_diode[1:0] 1, 3 vsystem[2:0] 1, 3 0x09 interrupt enable en_therm_lim_int en_wd_int en_tsd_int en_thr_int en_bat_int en_chg_int en_vin_int 0x0a interrupt active therm_lim_int wd_int tsd_int thr_int bat_int chg_int vin_int 0x0b charger status 1 vin_ov vin_ok vin_ilim therm_lim chdone charger_status[2:0] 0x0c charger status 2 thr_status[2:0] rch_lim_info battery_status[2:0] 0x0d fault bat_shr 1 tsd 130c 1 tsd 140c 1 0x10 battery short tbat_shr[2:0] 1 vbat_shr[2:0] 1 0x11 iend iend[2:0] 1, 3 c/20 eoc 1 c/10 eoc 1 c/5 eoc 1 sys_en_set[1:0] 1, 3 1 these bits reset to default i 2 c values when vinx is connected or disconnected. 2 the default i 2 c values of these bits are partially factory programmable. 3 the default i 2 c values of these bits ar e fully factory programmable.
ADP5063 data sheet rev. 0 | page 28 of 44 register bit descrip tions in table 18 through tabl e 33 , the following abbreviations are used: r is read only, w is write only, r/w is read/write, and n/a means not applicable. table 18 . manufacturer and model id, register address 0x00 bit no. bit name access default description [ 7:4] manuf[3:0] r 0001 the 4 - bit manufacturer identification bus [ 3:0] model[3:0] r 1001 the 4- bit model identification bus table 19. silicon revision, register address 0x01 bit no. bit name access default description [ 7:4] not used r [ 3:0] rev[3:0] r 0111 the 4 - bit sili con revision identification bus table 20. vinx pin settings, register address 0x02 bit no. bit name access default description [ 7:4] not used r [ 3:0] ilim[3:0] r/w 0000 = 100 ma vinx input current - limit programming bus. the current into vinx can be limited to the following programmed values: 0000 = 100 ma. 0001 = 150 ma. 0010 = 200 ma. 0011 = 250 ma. 0100 = 300 ma. 0101 = 400 ma. 0110 = 500 ma. 0111 = 600 ma. 1000 = 700 ma. 1001 = 800 ma. 1010 = 900 ma. 1011 = 1000 ma. 1100 = 1200 ma. 1101 = 1500 ma. 1110 = 1800 ma. 1111 = 2100 ma.
data sheet ADP5063 rev. 0 | page 29 of 44 table 21 . termination settings, register address 0x03 bit no. bit name access default description [7:2] vtrm[5:0] r/w 000101 = 3.60 v termination voltage programming bus. the values of the float ing voltage can be programmed to the following values: 000101 = 3.60 v . 000110 = 3.62 v . 000111 = 3.64 v . 001000 = 3.66 v . 001001 = 3.68 v . 001010 = 3.70 v . 001011 = 3.72 v . 001100 = 3.74 v . 001101 = 3.76 v . 001110 = 3.78 v . 001111 = 3.80 v . 010000 = 3.82 v . 010001 = 3.84 v . 010010 = 3.86 v . 010011 = 3.88 v . 010100 = 3.90 v . 010101 = 3.92 v . 010110 = 3.94 v . 010111 = 3.96 v . 011000 = 3.98 v . 011001 = 4.00 v . 011010 = 4.02 v . 011011 = 4.04 v . 011100 = 4.06 v . 011101 = 4.08 v . 011110 = 4.10 v . 011111 = 4.12 v . 100000 = 4.14 v . 100001 = 4.16 v . 100010 = 4.18 v . 100011 = 4.20 v . 100100 = 4.22 v . 100101 = 4.24 v . 100110 = 4.26 v . 100111 = 4.28 v . 101000 = 4.30 v . 101001 = 4.32 v . 101010 = 4.34 v . 101011 = 4.36 v . 101100 = 4.38 v . 101101 = 4.40 v . 101110 = 4.42 v . 101111 = 4.44 v . 110000 = 4.44 v . 110001 = 4.46 v . 110010 = 4.48 v . 110011 to 111111 = 4.50 v. [ 1:0] chg_vlim[1:0] r/w 0 0 = 3.2 v charging voltage limit programming bus. the values of the charging voltage limit can be programmed to the following values: 00 = 3.2 v . 01 = 3.4 v . 10 = 3.7 v . 11 = 3.8 v .
ADP5063 data sheet rev. 0 | page 30 of 44 table 22 . charging current settings, register address 0x04 bit no. bit name access default description 7 not used r [ 6 :2 ] ichg[4:0] r/w 01110 = 750 ma fast charge current programming bus. the values of the constant current charge can be programmed to the the following values: 00000 = 50 ma. 00001 = 100 ma. 00010 = 150 ma. 00011 = 200 ma. 00100 = 250 ma. 00101 = 300 ma. 00110 = 350 ma. 00111 = 400 ma. 01000 = 450 ma. 01001 = 500 ma. 01010 = 550 ma. 01011 = 600 ma. 01100 = 650 ma. 01101 = 700 ma. 01110 = 750 ma. 01111 = 800 ma. 10000 = 850 ma. 10001 = 900 ma. 10010 = 950 ma. 10011 = 1000 ma. 10100 = 1050 ma. 10101 = 1100 ma. 10110 = 1200 ma. 10111 to 11111 = 1300 ma. [ 1:0] itrk_dead[1:0] r/w 10 = 20 ma trickle and weak charge current programming bus. the values of the trickle and weak charge currents can be programmed to the following values: 00 = 5 ma. 01 = 10 ma. 10 = 20 ma. 11 = 80 ma. table 23 . voltage thresholds, register address 0x05 bit no. bit name access default description 7 dis_rch r/w 0 = recharge enabled 0 = recharge enabled. 1 = recharge disabled. [ 6:5] vrch[1:0] r/w 11 = 260 mv recharge voltage programming bus. the values of the recharge threshold can be programmed to the following values (note that the recharge cycle can be disabled in i 2 c by using the dis_rch bit): 00 = 80 mv. 01 = 140 mv. 10 = 200 mv. 11 = 260 mv.
data sheet ADP5063 rev. 0 | page 31 of 44 bit no. bit name access default description [ 4:3] vtrk_dead[1:0] r/w 00 = 2.0 v trickle to fast charge dead battery voltage programming bus. the values of the trickle to fast charge threshold can be programmed to the following values: 00 = 2.0 v. 01 = 2.5 v. 10 = 2.6 v. 11 = 2.9 v. [ 2:0] vweak[2:0] r/w 011 = 3.0 v weak battery voltage rising threshold. 000 = 2.7 v. 001 = 2.8 v. 010 = 2.9 v. 011 = 3.0 v. 100 = 3.1 v. 101 = 3.2 v. 110 = 3.3 v. 111 = 3.4 v. table 24. timer settings, register address 0x06 bit no. bit name access default description [ 7:6] not used 5 en_tend r/w 1 0 = c harge complete timer , t end , disabled . a 31 ms deglitch timer remain s on. 1 = charge complete timer enabled. 4 en_chg_timer r/w 1 0 = trickle/fast charge timer dis abled. 1 = trickle/fast charge timer en abled. 3 chg_tmr_period r/w 1 trickle and fast charge timer period. 0 = 30 sec t rickle charge timer and 300 - minute fast charge timer . 1 = 60 sec t rickle charge timer and 600 - minute fast charge timer . 2 en_wd r/w 0 0 = w atchdog timer is disabled even when bat_sns exceeds v weak . 1 = w atchdog timer safety timer is enabled. 1 wd_period r/w 0 watchdog safety timer period. 0 = 32 sec w atchdog timer and 40- minute safety timer . 1 = 64 sec w atchdog timer and 40- minute safety timer . 0 reset_wd w 0 when reset_wd is set to logic h igh by i 2 c, the watchdog safety timer is reset . table 25 . functional settings 1, register address 0x07 bit no. bit name access default description 7 not used 6 dis_ic1 r/w 0 0 = n ormal operation. 1 = the ADP5063 is disabled ; v vinx must be v iso_bx < v vinx < 5.5 v. 5 en_bmon r/w 0 0 = w hen v vinx < v vin_ok _rise or v vin_ok_fall , the battery monitor is disabled. when v vinx = 4 v to 6.7 v, the battery monitor is enabled regardless of the en_bmon state . 1 = the battery monitor is enabled even when the voltage at the vinx pins is below v vin_ok . 4 en_thr r/w 0 0 = w hen v vinx < v vin_ok_rise or v vin_ok_fall , the thr current source is disabled. when v vinx = 4 v to 6.7 v, the thr current source is enabled regardless of the en_thr state. 1 = thr current source is enabled even when the voltage at the vinx pins is below v vin_ok_rise or v vin_ok_fall . 3 dis_ldo r/w 0 0 = ldo is enabled. 1 = ldo is off. in addition, i f en_chg = low, the battery isolation fet is on. if en_chg = high , the battery isolation fet is off.
ADP5063 data sheet rev. 0 | page 32 of 44 bit no. bit name access default description 2 en_eoc r/w 1 0 = e nd of charge not allowed. 1 = end of charge allowed. 1 not used 0 en_chg r/w 0 0 = b attery charging is disabled. 1 = battery charging is enabled. table 26. functional settings 2, register address 0x08 bit no. bit name access default description 7 en_jeita r/w 0 = jeita disabled 0 = jeita compliance of the li - ion temperature battery charging specifications is disabled. 1 = jeita compliance enabled. 6 jeita_select r/w 0 = jeita1 0 = jeita1 is selected. 1 = jeita2 is selected. 5 en_chg_vlim r/w 0 0 = c harging voltage limit disabled. 1 = voltage limit enabled . the charger prevents charging until the battery voltage drops below the v chg_vlim threshold. [ 4:3 ] ideal_diode[1:0] r/w 00 00 = ideal diode operates constantly when v iso_sx < v iso_bx . 01 = ideal diode operates when v iso_sx < v iso_bx and v bat_sns > v weak . 10 = ideal diode is disabled. 11 = ideal diode is disabled. [ 2:0] vsystem[2:0] r/w 000 = 4.3 v s ystem voltage programming bus. the values of the system voltage can be programmed to the following values: 000 = 4.3 v. 001 = 4.4 v. 010 = 4.5 v. 011 = 4.6 v. 100 = 4.7 v. 101 = 4.8 v. 110 = 4.9 v. 111 = 5.0 v. table 27. interrupt enable, register address 0x09 bit no. bit name access default description 7 not used 6 en_therm_lim_int r/w 0 0 = i sothermal charging interrupt is disabled. 1 = isothermal charging interrupt is enabled. 5 en_wd_int r/w 0 0 = w atchdog alarm interrupt is disabled. 1 = watchdog alarm interrupt is enabled. 4 en_tsd_int r/w 0 0 = o vertemperature interrupt is disabled. 1 = overtemperature interrupt is enabled. 3 en_thr_int r/w 0 0 = thr temperature thresholds interrupt is disabled. 1 = thr temperature thresholds interrupt is enabled. 2 en_bat_int r/w 0 0 = b attery voltage thresholds interrupt is disabled. 1 = battery voltage thresholds interrupt is enabled. 1 en_chg_int r/w 0 0 = c harger mode change interrupt is disabled. 1 = charger mode change interrupt is enabled. 0 en_vin_int r/w 0 0 = vinx pin voltage thresholds interrupt is disabled. 1 = vinx pin voltage thresholds interrupt is enabled.
data sheet ADP5063 rev. 0 | page 33 of 44 table 28 . interrup t active, register address 0x0a bit no. bit name access default description 7 not used 6 therm_lim_int r 0 0 = no interrupt. 1 = indicates an interrupt caused by isothermal charging. 5 wd_int r 0 0 = no interrupt. 1 = indicates an interrupt caused by the watchdog alarm. the watchdog timer expires within 2 sec o r 4 sec, depending on the watch dog period setting of 32 sec or 64 sec, respectively. 4 tsd_int r 0 0 = no interrupt. 1 = indicates an interrupt caused by an overtemperature fault. 3 thr_int r 0 0 = no interrupt. 1 = indicates an interrupt caused by thr temperature thresholds. 2 bat_int r 0 0 = no interrupt. 1 = indicates an interrupt caused by battery voltage thresholds. 1 chg_int r 0 0 = no interrupt. 1 = indicates an interrupt caused by a charger mode change. 0 vin_int r 0 0 = no interrupt. 1 = indicates an interrupt caused by vinx voltage thresholds. table 29. charger status 1, register address 0x0b bit no. bit name access default description 7 vin_ov r n/a 1 = the voltage at the vinx pins exceeds v vin_ov . 6 vin_ok r n/a 1 = the voltage at the vinx pins exceeds v vin_ok_rise and v vin_ok_fall . 5 vin_ilim r n/a 1 = the current into a vinx pin is limited by the high voltage blocking fet and the charger is not running at the full programmed i chg . 4 therm_lim r n/a 1 = the charger is not running at the full programmed i chg but is limited by the die temperature. 3 chdone r n/a 1 = the end of a charge cycle has been reached. this bit latches on, in that it does not reset to low when the v rch threshold is breached. [ 2:0] cha r ger_status[2:0] r n/a charger status bus. 000 = off. 001 = trickle charge. 010 = fast charge (cc mode). 011 = fast charge (cv mode). 100 = charge complete. 101 = ldo mode. 110 = trickle or fast charge timer expired. 111 = battery detection.
ADP5063 data sheet rev. 0 | page 34 of 44 table 30. charger status 2, register address 0x0c bit no. mnemonic access default description [ 7:5] thr_status[2:0] r n/a thr pin status. 000 = off. 001 = battery cold. 010 = battery cool. 011 = battery warm. 100 = battery hot. 111 = thermistor ok. 4 not u sed 3 rch_lim_info r n/a the recharge limit information function is activated wh en dis_rch is logic high and charger_status[2:0] = 100 (binary). the rch_lim_info bit informs the system that a recharge cycle is required. 0 = v bat_sns > v rch 1 = v bat_sns < v rch [ 2:0] battery_status[2:0] r battery status bus. 000 = battery monitor off. 001 = no battery. 010 = v bat_sns < v trk_dead . 011 = v trk_dead v bat_sns < v weak . 100 = v bat_sns v weak . table 31 . fault , 1 register address 0x0d bit no. bit name access default description [ 7:4] not u sed 3 bat_shr r/w 0 0 = no fault. 1 = indicates detection of a battery short. 2 not u sed r/w 1 tsd 130c r/w 0 0 = no fault. 1 = indicates an overtemperature (lower) fault. 0 tsd 140c r/w 0 0 = no fault. 1 = indicates an overtemperature fault. 1 to reset the fault bits in the fault register, cycle the power on vinx or write the corresponding i 2 c bit high. table 32 . battery short, register address 0x10 bit no. bit name access default description [ 7:5] tbat_shr[2:0] r/w 100 = 30 sec battery short timeout timer . 000 = 1 sec. 001 = 2 sec. 010 = 4 sec. 011 = 10 sec. 100 = 30 sec. 101 = 60 sec. 110 = 120 sec. 111 = 180 sec. [ 4:3] not used [ 2:0] vbat_shr[2:0] r/w 100 = 2.4 v batter y short voltage threshold level . 000 = 2.0 v. 001 = 2.1 v. 010 = 2.2 v. 011 = 2.3 v. 100 = 2.4 v. 101 = 2.5 v. 110 = 2.6 v. 111 = 2.7 v.
data sheet ADP5063 rev. 0 | page 35 of 44 table 33. iend , register address 0x11 bit no. bit name access default description [ 7:5] iend[2:0] r/w 010 = 52.5 ma termination current programming bus. the values of the termination current can be programmed to the following values: 000 = 12.5 ma. 001 = 32.5 ma. 010 = 52.5 ma. 011 = 72.5 ma. 100 = 92.5 ma. 101 = 117.5 ma. 110 = 142.5 ma. 111 = 170.0 ma. 4 c/20 eoc r/w 0 the c/20 eoc bit has priority over the other settings (c/5 eoc, c/10 eoc, and iend[2:0]). 0 = not active. 1 = the termination current is ichg[4:0] 20 with the following limitations: minimum value = 12.5 ma. maximum value = 170 ma. 3 c/10 eoc r/w 0 the c/10 eoc bit has priority over the other termination current settings ( c/5 eoc and i end[2:0] ), but it does not have priority over the c/20 eoc setting. 0 = not active. 1 = the termination current is ichg[4:0] 10 , unless c/20 eoc is high. the termination current is limited to the following values: minimum value = 12.5 ma. maximum value = 170 ma. 2 c/5 eoc r/w 0 the c/5 eoc bit has priority over the other termination current settings ( iend[2:0] ) but it does not have priority over the c/20 eoc setting or the c/10 eoc setting. 0 = not active. 1 = the termination current is ichg[4:0] 5 , unless the c/20 eoc or the c/10 eoc bit is high. the termination current is limited to the following values: minimum value = 12.5 ma. maximum value = 170 ma. 1:0 sys_en_set[1:0] r/w 00 selects the operation of the system enable pin (sys_en). 00 = sys_en is activated when the ldo is active and the system voltage is available. 01 = sys_en is activated by the iso_bx voltage , the battery charging mode. 10 = sys_en is activated and the isolation fet is disabled when the battery drops below v weak . 1 11 = sys_en is active in ldo mode when the charger is disabled. sys_en is active in charging mode when viso_bx v weak . 1 this option is active when vinx = 0 v and the battery monitor is activated from register 0x07, bit 5 (en_bmon).
ADP5063 data sheet rev. 0 | page 36 of 44 application s information external components iso_sx (v out ) capacitor selection to obtain stable operation of the ADP5063 in a safe way , the combined effective capacitance of the iso_sx capacitor and the system capacitance must not be less than 1 0 f and must not exceed 100 f at any point during operation. when choosing the capacitor value, it is also important to account for the loss o f capacitance caused by the output voltage dc bias. ceramic capacitors are manufa ctured with a variety of dielec trics, each with a different behavior over temperature and applied v oltage. capacitors must have a dielectric that is adequate to ensure the minimum capacitance over the necessary temperature range and dc bias conditions. x5r or x7r dielectrics with a voltage rating of 6.3 v or higher are recommended for best performance. y5v and z5u dielectrics are not recommended for use with any dc - to - dc co nverter because of their poo r temper ature and dc bias characteristics. the worst - case capacitance , accounting for capacitor variation over temperature, component tolerance, and voltage , is calcu - lated using the following equation: c eff = c out (1 ? tempco ) (1 ? tol ) where: c eff is the effective capacitance at the operating voltage. tempco is the worst - case capacitor temperature coefficient. tol is the worst - case component tolerance. in this example, the worst - case temperature coefficient (tempco) over the range of ? 40c to +85c is assumed to be 15% for an x5r dielectric. the tolerance of the capacitor (tol) is assumed to be 10%, and c out is 16 f at 4.2 v, as shown in figure 35. figure 35 . murata grm31cr61a226ke19 capacitance vs. bias voltage substituting these values in the equation yields c eff = 16 f (1 ? 0.15) (1 ? 0.1 ) 12.24 f to guarantee the performance of the charger in various operati ng modes , including trickle charge, constant current charge, and constant voltage charge, it is imperative that the effects of dc bias, temperature, and tolerances on the behavior of the capaci - tors be evaluated for each appli cation. splitting iso_sx capacitance in many application s, the total iso_sx capacitance consist s of a number of capacitors. the system voltage node (iso_sx) usually supplies a single regulator or a number of ics and regulators, each of which requires a cap acitor close to its power supply input (see figure 36 ). the capacitance close to the ADP5063 iso_sx output must be at least 5 f , as long as the total effective capacitance is at least 1 0 f at any point during operation. figure 36 . splitting iso_sx capacitance iso_bx and iso_sx capacitor selection the iso_bx an d the iso_sx effective capacitance (including temperature and dc bias effects) must not be less than 10 f at any point during operation. typically , a nominal capacitance of 22 f is required to fullfill the condition at all points of operation. suggestions for iso_bx and iso_sx capacitor s are listed in table 34. cbp capacitor selection the i nternal supply voltage of the ADP5063 is equipped with a noise suppressing capacitor at the cbp terminal. do not allow cbp capacitance to exceed 1 4 0 nf at any point during operation. do not connect any external voltage source, any resistive load , or any other current load to the cbp terminal. suggestions for a cbp capacitor are listed in table 35. 2 0 2 5 3 0 3 5 4 0 4 5 5 0 5 5 6 0 0 1 2 3 4 5 c a p ac i t anc e ( f ) dc b i a s vo l t a g e (v) 1 1593-041 ADP5063 ic1 ic2 iso_sx vin1 vin2 c in2 c iso_sx > 5f c iso_bx 10f sum of effective capacitances on iso_sx node > 10f + iso_bx c in1 1 1593-038
data sheet ADP5063 rev. 0 | page 37 of 44 vinx capacitor selection according to the usb 2.0 specification, usb peripherals have a detectabl e change in capacitance on vbus when they are attached to a usb port . the peripheral device vbus bypass capacitance must be at least 1 f but not larger than 10 f. the vinx input of the ADP5063 is tolerant of voltages as high as 20 v ; however, i f an application requires exposing the vinx input to voltages of up to 20 v, the voltage range of the capacitor must also be above 20 v. suggestions for a vinx capacitor are given in table 36 . w hen using ceramic capacitors , a higher voltage range is usually achieved by selecting a component with larger physical dimensions. in application s where lower than 20 v at vinx input voltages can be guaranteed, smaller output capacitors can be used accordingly. table 34 . iso_bx and iso_sx capacitor suggestions vendor part number value voltage sie murata grm31cr61a226ke19 22 f 10 v 1206 murata grm31cr60j226me19 22 f 6.3 v 1206 tdk c3216x5r0j226m 22 f 6.3 v 1206 t aiyo - y uden jmk316abj226kl -t 22 f 6.3 v 1206 table 35. cbp capacitor suggestions vendor part number value voltage sie murata grm155r70j104ka01 100 n f 6.3 v 0402 tdk c1005x7r1a104k050 bb 10 0 nf 1 0 v 0402 table 36 . vinx capacitor suggestions vendor part number value voltage sie murata grm21br61e106ma73 10 f 25 v 0805 tdk c2012x5r1e106k 10 f 25 v 0805
ADP5063 data sheet rev. 0 | page 38 of 44 pcb layout guideline s figure 37 . reference circuit diagram figure 38 . reference pcb floor p lan 9 vddio 10 11 13 14 19 7 6 1 17 20 5 3 18 vin1 to vin3 cbp scl sda iso_s1 to iso_s3 iso_b1 to iso_b3 sys_en agnd dig_io1 dig_io2 dig_io3 thr 4 bat_sns to mcu to mcu to mcu to mcu/nc to mcu/nc charger control block r5 ntc 10k? (optional) connect close to battery + 8 12 2 to mcu/nc 15 iled vled 16 vddio r4 10k? r2 1.5k? r1 1.5k? c4 10f grm21br6e106ma73 c1 100nf grm155r70j104ka01 vin = 4v to 7v c3 22f grm31cr60j226me19 c2 22f grm31cr60j22me19 ADP5063 20-lead lfcsp 1 1593-040 vinx pgnd pgnd cbp pgnd iso_bx iso_sx c4: 10f, 25v/x5r, 0805 c3: 22f, 16v/x5r, 1206 c2: 22f, 16v/x5r, 1206 c1: 100nf, 16v/x7r, 0402 1 1593-100
data sheet ADP5063 rev. 0 | page 39 of 44 power dissipation an d thermal considerat ions charger power dissip ation when the ADP5063 charger operates at high ambient tempera - tures and at maximum current charging and loading conditions, the junction temperature can reach the max imum allowable operating limit of 125c . when the junction temperature exceeds 140c, the ADP5063 turns off , allowing the device to cool down. when the die temperature falls below 110c and the tsd 140c fault bit in register 0x0d is cleared by an i 2 c write, the ADP5063 resumes normal operation. this section pr ovides guidelin es to calculate the power dissi pated in the device to ensure that the ADP5063 operates below the maximum allowable junction temperature. to determine the available power dissipation in different operating modes under various operating conditions , use equation 1 through equation 4 : p d = p ldofet + p isofet (1) w here : p ldofet is the power dissipated in the input ldo fet. p isofet is the power dissipated in the battery isolation f e t. calculate the p ower dissipation in the ldo fet and the battery isolation fet using equation 2 and equation 3 . p ldofet = (v in C v iso_sx ) (i chg + i load ) (2) p isofet = (v iso_sx C v iso_b x ) i chg (3) w here : v in is the input voltage at the vinx pins. v iso_sx is the system voltage at the iso_sx pins. i chg is the battery charge current. i load is the system load current from the iso_sx pins. v iso_b x is the battery voltage at the iso_bx pins. ldo mode the system regulation voltage is user - programmable from 4.3 v to 5.0 v. in ldo mode (charging disabled, en_chg = low) , calculation of the total power dissipation is simplified , assuming that all current is drawn from the vin x pins and the battery is not shared with iso_sx. p d = (v in C v iso_sx ) i load charging mode in charging mode , the voltage at the iso_sx pins depends on the battery level. when the battery voltage is lower than v iso_sfc (typically 3. 4 v) , the voltage drop over the battery isolation fet is higher and the power dissipation must be calculated using e quation 3. when the battery voltage level reaches v iso_sfc , the power dissipation can be calculated using e quation 4. p isofet = r dson _ iso i chg (4) w here : r dson_iso is the on resistance of the battery isolation fet ( typically 110 m? during charging) . i chg is the battery charge current. the thermal control loop of the ADP5063 automatically limit s the charge current to maintain a die temperature below t lim (typically 115c). the most intuitive and practical way to calculate the power dissipation in the ADP5063 device is to measure the power dissipated a t the input and all of the outputs. perform the measurements at the worst - case conditions (voltages, currents, and temperature). the difference between input and output power is the power that is dissipated in the device. junction temperature in cases whe re the board temperature, t a , is known, the thermal resistance parameter, ja , can be used to estimate the junction temperature rise. t j is calculated from t a and p d using the formula t j = t a + (p d ja ) (5) the typical ja value for the 20 - lead lf csp is 35. 6 c/w (see table 5 ). a very important factor to consider is that ja is based on a 4 - layer, 4 in 3 in, 2.5 oz . copper board as per jedec standard, and real - world applications may use different sizes and layers. it is important to maximize the copper to remove the heat from the device. copper exposed to air dissipates heat better than copper used in the inner layer s. if the case temperature can be measured, the junction temperature is calculated by t j = t c + (p d jc ) (6) where t c is the case temperature and jc is the junction - to - case thermal resistance provided in table 5 . the reliable operation of the charger can be achieved only if the estimated die junction temperature of the ADP5063 (equation 5) is less than 12 5c. reliability and mean time between failures (mtbf) are great ly affected by increas ing the junction temperature. additional information about product reliability can be found in the adi reliability handbook located at the following url: http://www.analog.com/reliability_handbook .
ADP5063 data sheet rev. 0 | page 40 of 44 factory - programmable options charger options table 37 to tabl e 49 list the factory - programmable options of the ADP5063 . in each of these tables , the selection column represents the default setting of m odel ADP5063 ac pz - 1 - r7. table 37 . default termination voltage option selection 000 = 4.20 v 001 = 3.60 v 001 = 3.60 v 010 = 3.70 v 011 = 3.80 v 100 = 3.90 v 101 = 4.00 v 110 = 4.10 v 111 = 4.40 v table 38 . default fast charge current option selection 000 = 500 ma 001 = 300 ma 010 = 550 ma 011 = 600 ma 100 = 750 ma 100 = 750 ma 101 = 900 ma 110 = 1300 ma 111 = 1300 ma table 39 . default end of charge current option selection 000 = 52.5 ma 000 = 52.5 ma 001 = 72.5 ma 010 = 12.5 ma 011 = 32.5 ma 100 = 142.5 ma 101 = 167.5 ma 110 = 92.5 ma 111 = 117.5 ma table 40 . default trickle to fast charge threshold option selection 00 = 2.5 v 01 = 2.0 v 01 = 2.0 v 10 = 2.9 v 11 = 2.6 v table 41 . default system voltage option selection 000 = 4.3 v 000 = 4.3 v 001 = 4.4 v 010 = 4.5 v 011 = 4.6 v 100 = 4.7 v 101 = 4.8 v 110 = 4.9 v 111 = 5.0 v table 42 . thermistor resistance option selection 0 = 10 k 0 = 10 k 1 = 100 k table 43 . thermistor beta value option selection 0100 = 3150 0100 = 3150 0101 = 3350 0110 = 3500 0111 = 3650 1000 = 3850 1001 = 4000 1010 = 4200 1011 = 4400 table 44 . dis_ic1 mode select option selection 0 = dic_ic1 mode select, vinx current = 280 a, iso_b x can float, no leak to iso_bx 0 = dic_ic1 mode select, vinx current = 280 a, iso_bx can float, no leak to iso_bx 1 = dic_ic1 mode sele ct, vinx current = 110 a, supply switch leaks from vinx to iso_bx table 45 . trickle or fast charge timer fault operation option selection 0 = a fter timeout ldo off, charging off 1 = a fter timeout ldo mode active, charging off 1 = after timeout ldo mode active, charging off
data sheet ADP5063 rev. 0 | page 41 of 44 i 2 c register defaults table 46. i 2 c register default settings bit name i 2 c register address, bit location option selection chg_vlim [1:0] address 0x03 , b it s[ 1 : 0] 0 = limit 3.2 v 0 = limit 3.2 v 1 = limit 3.7 v dis_rch address 0x05, b it 7 0 = rec harge enabled 0 = recharge enabled 1 = recharge disabled en_wd address 0x06, b it 2 0 = watchdog disabled 0 = disabled 1 = watchdog enabled dis_ic1 address 0x07, b it 6 0 = not activated 0 = not activated 1 = activated en_chg address 0x07, b it 0 0 = charging disabled 0 = charging disabled 1 = charging enabled en_jeita address 0x08, b it 7 0 = jeita function disabled 0 = jeita function disabled 1 = jeita function enabled jeita_select address 0x08, b it 6 0 = jeita1 charging 0 = jeita1 charging 1= jeita2 charging en_chg_vlim address 0x08, b it 5 0 = limit disabled 0 = limit disabled 1 = limit enabled ideal_diode[1:0] address 0x08, b it s[ 4:3] 00 = i deal diode operates when v iso_sx < v iso_bx 00 = ideal diode operates when v iso_sx < v iso_bx 01 = i deal diode operates when v iso_sx < v iso_bx and v bat_sns > v weak 10 = i deal diode is disabled 11 = i deal diode is disabled digital input and output options table 47. i 2 c address 0x11, b its[ 1:0 ] , sys_ en _set default option selection (default) 00 = sys_en is activated when ldo is active and system voltage is available . 00 01 = sys_en is activated by iso_bx voltage; b attery charging mode . 10 = sys_en is activated and the i solation fet is disabled when the battery drops below v weak 1 . 11 = sys_en is active in ldo mode when the charger is disabled. sys_en is active in charging mode when v iso_bx v weak . 1 this option is active when vinx = 0 v and the battery monitor is activated from register 0x07, bit d5 (en_bmon).
ADP5063 data sheet rev. 0 | page 42 of 44 dig_io1, dig_io2, and dig_io3 options table 48 . dig_io1 polarity table 49 . dig_iox option s option dig_io1 function dig_io2 function dig_io3 function selection 0000 i vinx limit disable ic1 charging disable/enable low = 100 ma low = not activated low = charging disable high = 500 ma high = activated high = charging enabled 0010 i vinx limit i vinx limit disable ic1 low = 100 ma not applicable low = not activated high = 500 ma high = i vinx limit at 1500 ma high = activated 0011 i vinx limit i vinx limit fast charge current low = 100 ma not applicable low = ichg[4:0] high = 500 ma high = i vinx limit at 1500 ma high = ichg[4:0] 2 0100 i vinx limit i vinx limit ldo low = 100 ma not applicable low = ldo active high = 500 ma high = i vin limit at 1500 ma high = ldo disabled 0101 i vinx limit i vinx limit charging 0101 low = 100 ma not applicable low = charging disabled high = 500 ma high = i vinx limit at 1500 ma high = charging enabled 0110 i vinx limit recharge charging low = 100 ma not applicable low = charging disabled high = 500 ma high = disable recharge high = charging enabled 0111 charging disable ic1 recharge low = charging disabled low = not activated not applicable high = charging enabled high = activated high = disable recharge 1000 i vinx limit i vinx limit interrupt output low = 100 ma not applicable not applicable high = 500 ma high = i vinx limit 1500 ma not applicable 1001 i vinx limit charging interrupt output low = 100 ma low = charging disabled not applicable high = 500 ma high = charging enabled not applicable 1010 i vinx limit disable ic1 interrupt output low = 100 ma low = not activated not applicable high = 500 ma high = activated not applicable 1011 i vinx limit recharge interrupt output low = 100 ma not applicable not applicable high = 500 ma high = disable recharge not applicable 1100 i vinx limit fast charge current interrupt output low = 100 ma low = ichg not applicable high = 500 ma high = ichg[4:0] 2 not applicable 1101 i vinx limit ldo interrupt output low = 100 ma low = ldo active not applicable high = 500 ma high = ldo disabled not applicable 1110 i vinx limit charging interrupt output not applicable low = charging disabled not applicable high = i vinx limit 1500 ma high = charging enabled not applicable 1111 disable ic1 charging interrupt output low = not activated low = charging disabled not applicable high = activated high = charging enabled not applicable option selection 0 = dig_io1 polarity, high active operation 0 = high active 1 = dig_io1 polarity, low active operation
data sheet ADP5063 rev. 0 | page 43 of 44 packaging and ordering information outline dimensions figure 39 . 20- lead lead frame chip scale package [lfcsp_wq] 4 mm 4 mm body, very very thin quad (cp - 20 - 8) dimensions shown in millimeters ordering guide model 1 , 2 temperature range (junction) package description package option ADP5063 ac p z -1-r7 C 40c to +125c 20-l ead lead frame chip scale package [ lfcsp _wq ] cp -20-8 ADP5063 cp - evalz evaluation board 1 z = rohs compliant part. 2 for additional factory - programmable options, contact an analog devices, inc., local sales or distribution representative . 0.50 bsc 0.50 0.40 0.30 0.30 0.25 0.18 compliant to jedec standards mo-220-wggd. 020509-b bot t om view top view exposed pa d pin 1 indic a t or 4.10 4.00 sq 3.90 sea ting plane 0.80 0.75 0.70 0.05 max 0.02 nom 0.20 ref 0.25 min coplanarity 0.08 pin 1 indic a t or 2.75 2.60 sq 2.35 for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. 1 20 6 10 11 15 16 5
ADP5063 data sheet rev. 0 | page 44 of 44 notes i 2 c refers to a communications protocol originally developed by philips semiconductors (now nxp semiconductors). ? 2013 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d11593 - 0 - 7/13(0)

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